1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a memory cell of a semiconductor memory device and a method for driving the memory cell.
2. Description of the Related Art
Generally, a non-volatile memory device, such as an Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable ROM (EEPROM) and flash memory, is used for a main control unit (MCU), a power integrated circuit (IC), a display driving chip, a CMOS image sensor, and the like. However, fabrication of a non-volatile memory device may include additional processes that cause long turn-around time (TAT), an increase in the fabrication complexity, and a decrease in the fabrication reliability and cost. Therefore, a One-Time Programmable (OTP) memory device fabricated without an additional process is widely used. An OTP memory device may be programmed with a data, for example, only once per memory cell, and the programmed data is retained even though power is turned off. The OTP memory device is used for storing trimming information, security identification (ID), chip ID, and calibration data or used as a redundancy memory device of a main memory device.
Meanwhile, the OTP memory device may be divided into a memory device that may be designed based on an electrical fuse scheme logic process and a memory device that may be designed based on an anti-fuse scheme logic process.
Memory cells of the OTP memory device of an anti-fuse scheme are programmed by applying a higher voltage than a breakdown voltage to a thin gate oxide layer for an electrical short circuit. In other words, the OTP memory device of an anti-fuse scheme uses a high voltage during a program operation. For example, a voltage of approximately 5.5V to approximately 8.5V is used as a program voltage. The memory cells of the OTP memory device of an anti-fuse scheme have high data reliability and yield characteristics, but the memory cells of the OTP memory device of an anti-fuse scheme may have restrictive usage in a low voltage environment, such as a CMOS device. This is because a constituent element such as a logic transistor does not endure high program voltage.
On the other hand, memory cells of the OTP memory device of an electrical fuse scheme blow and cut off an electrical fuse by applying an over-current of approximately 10 mA to approximately 20 mA to a polysilicon gate. For example, the memory cells of the OTP memory device of an electrical fuse scheme are designed to be programmed with a program voltage of approximately 3.3V.
FIG. 1 illustrates a memory cell of a conventional OTP memory device of an electrical fuse scheme.
Referring to FIG. 1, a memory cell structure 10 includes an electrical fuse 12 and an NMOS transistor 14. The electrical fuse 12 has its anode coupled with a bit line BL and a cathode coupled with a coupling node CN. The NMOS transistor 14 includes a gate coupled with a word line WL and a drain-source path coupled between the coupling node CN and a ground voltage VSS end.
Hereinafter, a method for driving the memory cell structure 10 having the above structure during a program operation and a read operation is described.
First, a program operation is described.
As a program voltage is applied to the bit line BL and the word line WL, a program current flows through the electrical fuse 12 and the NMOS transistor 14. When the program current flows for a given time, the electrical fuse 12 is blown and electrically disconnected. For example, the electrical fuse 12 has a resistance of approximately 50Ω to approximately 100Ω before the program operation while the electrical fuse 12 comes to have a resistance of approximately over 100 kφ after the program operation. As described above, the electrical fuse 12 is programmed to be any one between a conductive state and a highly resistive state.
Second, a read operation is described below.
When a read voltage is applied to the word line WL while the bit line BL is pre-charged with a given voltage, the pre-charged voltage level of the bit line BL is decreased or maintained depending on whether the electrical fuse 12 is programmed to be in the conductive state or the highly resistive state. Here, a data is outputted by sensing the state of the pre-charged voltage level of the bit line BL.
However, the memory cell structure 10 of the conventional semiconductor memory device using an electrical fuse may have its data reliability and yield characteristics lower than a memory cell structure of a semiconductor memory device of an anti-fuse scheme.
Therefore, a memory cell structure of a semiconductor memory device having excellent data reliability and yield characteristics, while having applicability to a low-voltage environment is being developed.